1. Technical Field
The present invention relates to a test apparatus and a test method for a memory. In particular, the present invention relates to a test apparatus and a test method for concurrently testing a plurality of memories under test.
2. Related Art
Conventional semiconductor memory test apparatuses are designed to concurrently test a plurality of memories under test, for the purpose of enhancing the test efficiency. Specifically, a conventional semiconductor memory test apparatus writes test data to each of the plurality of memories under test, and causes each of the memories under test to output the test data having been written therein. The semiconductor memory test apparatus then determines whether each outputted test data matches expected value data, in order to determine the acceptability of each memory under test.
When the memories under test are flash memories, the time required for testing the memories under test is not constant due to occurrence of writing/reading errors. In the conventional test apparatuses, various functions are provided to enhance the test efficiency, such as controlling memories under test having determined to fail a test at some stage of the test will stop being subjected to the further test stages, to make sure these failure memories under test will not obstruct the test of the other memories under test.
No prior art documents are recognized to date.
Some conventional test apparatuses occasionally own, for each of a plurality of memories under test, a circuit for controlling input/output (hereinafter referred to as “input/output circuit”) of test data to/from the memory under test. Then, the test apparatus can concurrently read test data from each of the memories under test, and determine the acceptability of the memories under test independently from each other. However, in such a configuration, the number of memories under test that can be tested at the same time is limited by the number of input/output circuits. A greater number of input/output circuits will be required if a greater number of memories under test are desired to be tested concurrently, thereby leading to increase in the dimension of the test apparatus.
In some tests, test data to be written can be the same for the plurality of memories under test. In such a test, test data outputted from a single input/output circuit is simply supplied to the plurality of memories under test that are bus connected to each other. This does not increase the number of required input/output circuits even if there is increase in number of memories under test, and can prevent increase in the dimension of the test apparatus. However, this configuration requires determining which memory under test has outputted which piece of test data. Conventional test apparatuses have coped with this problem by collecting and analyzing all the data after a test has ended, to determine which test data is read from which memory under test. This step can be time-consuming, to degrade the test efficiency.